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Research

Microarchitecture for Security

• Offensive side: New microarchitecture side/covert timing channels (attacks)
• Defensive side: Mitigation techniques for transient execution attacks like Spectre and Meltdown, Flush-based, eviction-based, and Rowhammer based attacks
• Performance-Security tradeoffs: Design of secure processors (Intel SGX kinda) and memory hierarchies keeping performance and security in mind.

Microarchitecture for Performance

• Memory hierarchy optimizations: Data prefetching, instruction prefetching, microarchitecure-interactions, shared resource management, front-end and back-end bottleneck mitigation techniques keeping performance and power in mind
• Architecture-OS interaction: TLB/Page-table-walker optimizations, memory hierarchy for virtualization, memory hierarchy for high-speed network I/O (Intel DDIO kinda), persistent memory optimizations (Intel Optane kinda)
• ML/RL for architecture: ML/RL for microarchitecture optimizations, Application specific microarchitecture

We maintain a strong collaboration with the SHARC group, combining expertise to drive innovation in hardware security and performance. Our research is generously supported by Intel Research, Google, Qualcomm, and NXP.

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